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NEW QUESTION: 1
Which statement is correct about the Cisco IOS Control Plane Protection feature?
A. The open-port option of a port-filtering policy allows access to all TCP/UDP based services that are configured on the router.
B. Disabling CEF will remove all active control-plane protection policies. Aggregate control-plane policies will continue to operate.?
C. Traffic that is destined to the router with IP options will be redirected to the host control plane.
D. Control Plane Protection is restricted to the IPv4 or IPv6 input path.
Answer: B
Explanation:
Control Plane Protection depends on Cisco Express Forwarding (CEF) for IP packet redirection. If you disable CEF globally, this will remove all active protect and policing policies configured on the control-plane subinterfaces. Aggregate control-plane interface policies will continue to function as normal.

NEW QUESTION: 2
After completing Discipline 4, Root Causes, of the 8D Troubleshooting Methodology, what is the next discipline to be completed?
A. Discipline 5 - Implement a Work-around
B. Discipline 5 - Choose Corrective Actions
C. Discipline 5 - Implement Corrective Actions
D. Discipline 5 - Prevent Recurrences
Answer: B

NEW QUESTION: 3

A. POWER7 processor mode
B. TPMD (Thermal Power Management Device)
C. CAPI
D. Energy Scale Technology
Answer: C
Explanation:
IT organizations must provide increased system performance as their workloads grow with demands for big data analysis, social media applications, continuous customer connectivity, and business-specific applications. Increases in processor performance alone cannot satisfy the workload demands, so solutions must also come from system-level advances such as hybrid computing, processing engine customization, and open platform development that enables cross-company innovation.
The Coherent Accelerator Processor Interface (CAPI) on IBM@ POWER8 systems provides solution architects with a new way to gain system-level performance. CAPI connects a custom acceleration engine to the coherent fabric of the POWER8 chip. The hybrid solution has a simple programming paradigm while delivering performance well beyond today's I/O attached acceleration engines.